INTEGRATED CIRCUIT LAYOUT AND METHOD FOR MANUFACTURING INTEGRATED CIRCUIT DEVICE USING THE INTEGRATED CIRCUIT LAYOUT

INTEGRATED CIRCUIT LAYOUT AND METHOD FOR MANUFACTURING INTEGRATED CIRCUIT DEVICE USING THE INTEGRATED CIRCUIT LAYOUT

An integrated circuit layout includes: a first chip area; and a second chip area, wherein the first chip area includes: a first main area including a first main pattern; a first mark area adjacent to the first main area, wherein a first mark pattern is formed in the first mark area; and a first dumm...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: PARK, Hyung Keun, JEONG, Hee, CHOI, Da Woon, SONG, Yun Kyoung, KIM, Bong Keun, NOH, Myung Soo
Format: Patent
Sprache:eng
Schlagworte:
BASIC ELECTRIC ELEMENTS
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
PHYSICS
SEMICONDUCTOR DEVICES
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Beschreibung
Zusammenfassung:An integrated circuit layout includes: a first chip area; and a second chip area, wherein the first chip area includes: a first main area including a first main pattern; a first mark area adjacent to the first main area, wherein a first mark pattern is formed in the first mark area; and a first dummy area including a first dummy pattern, wherein the second chip area includes: a second main area including a second main pattern; a second mark area adjacent to the second main area, wherein a second mark pattern is formed in the second mark area; and a second dummy area including a second dummy pattern, wherein the first and second mark patterns are used to check alignment states of the first chip area and the second chip area, respectively, and wherein each of the first and second mark patterns has a standard cell structure.