DIGITAL PHASE LOCKED LOOP AND METHODS OF OPERATING SAME

A digital phase-locked loop (PLL) includes: (i) a digitally controlled oscillator (DCO) configured to generate an oscillation signal having a frequency that is adjustable in response to a frequency control signal, (ii) a divider configured to generate a feedback signal in response to dividing a freq...

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Bibliographische Detailangaben
Hauptverfasser: Park, Jaewoo, Kwak, Myoungbo, Choi, Junghwan, Lee, Yongsun, Jung, Jinook
Format: Patent
Sprache:eng
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Zusammenfassung:A digital phase-locked loop (PLL) includes: (i) a digitally controlled oscillator (DCO) configured to generate an oscillation signal having a frequency that is adjustable in response to a frequency control signal, (ii) a divider configured to generate a feedback signal in response to dividing a frequency of the oscillation signal, (iii) a time-to-digital converter (TDC) configured to detect a phase difference between a reference signal and the feedback signal, and generate an error signal having a value that is a function of the phase difference, and (iv) a digital loop filter configured to generate the frequency control signal in response to the error signal and the oscillation signal.