DUTY CYCLE CALIBRATION CIRCUIT, CORRESPONDING TRANSMITTER, COMMUNICATION SYSTEM AND METHOD

In embodiments, a clock signal calibration circuit for communication transmitters includes a multiplexer that creates a combined output pattern from input data patterns in reaction to the clock signal's edges. It uses a calibration data pattern generator, which supplies two sequential patterns-the second being a shifted copy of the first-to the multiplexer. An averaging circuit then generates two averaged signals corresponding to these patterns. Duty cycle control circuitry corrects clock signal imbalances if these averaged signals are unequal, thus adjusting the duty cycle distortion to achieve an ideal 50% duty cycle.