METHOD OF MANUFACTURING FAN-OUT PACKAGING DEVICE AND FAN-OUT PACKAGING DEVICE MANUFACTURED THEREBY
Disclosed is a method of manufacturing a fan-out packaging device using wafer or panel level packaging including forming a base metal layer on a partial area of a fan-out packaging substrate, forming a first dielectric layer on the base metal layer, patterning the first dielectric layer to form a vi...
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creator | SUTARDJA, Sehat |
description | Disclosed is a method of manufacturing a fan-out packaging device using wafer or panel level packaging including forming a base metal layer on a partial area of a fan-out packaging substrate, forming a first dielectric layer on the base metal layer, patterning the first dielectric layer to form a via hole, forming a redistribution layer (RDL) on the first dielectric layer and the via hole, forming a second dielectric layer on the redistribution layer (RDL), and patterning the second dielectric layer to form a bump structure connected to the redistribution layer. |
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fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2024347433A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2024347433A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2024347433A13</originalsourceid><addsrcrecordid>eNrjZEjydQ3x8HdR8HdT8HX0C3VzdA4JDfL0c1dwc_TT9Q8NUQhwdPZ2dAeJuLiGeTq7Kjj6ueCWRJjh6qIQ4uEa5OoUycPAmpaYU5zKC6W5GZTdXEOcPXRTC_LjU4sLEpNT81JL4kODjQyMTIxNzE2MjR0NjYlTBQB-rjSK</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>METHOD OF MANUFACTURING FAN-OUT PACKAGING DEVICE AND FAN-OUT PACKAGING DEVICE MANUFACTURED THEREBY</title><source>esp@cenet</source><creator>SUTARDJA, Sehat</creator><creatorcontrib>SUTARDJA, Sehat</creatorcontrib><description>Disclosed is a method of manufacturing a fan-out packaging device using wafer or panel level packaging including forming a base metal layer on a partial area of a fan-out packaging substrate, forming a first dielectric layer on the base metal layer, patterning the first dielectric layer to form a via hole, forming a redistribution layer (RDL) on the first dielectric layer and the via hole, forming a second dielectric layer on the redistribution layer (RDL), and patterning the second dielectric layer to form a bump structure connected to the redistribution layer.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2024</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20241017&DB=EPODOC&CC=US&NR=2024347433A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76289</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20241017&DB=EPODOC&CC=US&NR=2024347433A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>SUTARDJA, Sehat</creatorcontrib><title>METHOD OF MANUFACTURING FAN-OUT PACKAGING DEVICE AND FAN-OUT PACKAGING DEVICE MANUFACTURED THEREBY</title><description>Disclosed is a method of manufacturing a fan-out packaging device using wafer or panel level packaging including forming a base metal layer on a partial area of a fan-out packaging substrate, forming a first dielectric layer on the base metal layer, patterning the first dielectric layer to form a via hole, forming a redistribution layer (RDL) on the first dielectric layer and the via hole, forming a second dielectric layer on the redistribution layer (RDL), and patterning the second dielectric layer to form a bump structure connected to the redistribution layer.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2024</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZEjydQ3x8HdR8HdT8HX0C3VzdA4JDfL0c1dwc_TT9Q8NUQhwdPZ2dAeJuLiGeTq7Kjj6ueCWRJjh6qIQ4uEa5OoUycPAmpaYU5zKC6W5GZTdXEOcPXRTC_LjU4sLEpNT81JL4kODjQyMTIxNzE2MjR0NjYlTBQB-rjSK</recordid><startdate>20241017</startdate><enddate>20241017</enddate><creator>SUTARDJA, Sehat</creator><scope>EVB</scope></search><sort><creationdate>20241017</creationdate><title>METHOD OF MANUFACTURING FAN-OUT PACKAGING DEVICE AND FAN-OUT PACKAGING DEVICE MANUFACTURED THEREBY</title><author>SUTARDJA, Sehat</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2024347433A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2024</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>SUTARDJA, Sehat</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>SUTARDJA, Sehat</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>METHOD OF MANUFACTURING FAN-OUT PACKAGING DEVICE AND FAN-OUT PACKAGING DEVICE MANUFACTURED THEREBY</title><date>2024-10-17</date><risdate>2024</risdate><abstract>Disclosed is a method of manufacturing a fan-out packaging device using wafer or panel level packaging including forming a base metal layer on a partial area of a fan-out packaging substrate, forming a first dielectric layer on the base metal layer, patterning the first dielectric layer to form a via hole, forming a redistribution layer (RDL) on the first dielectric layer and the via hole, forming a second dielectric layer on the redistribution layer (RDL), and patterning the second dielectric layer to form a bump structure connected to the redistribution layer.</abstract><oa>free_for_read</oa></addata></record> |
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subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
title | METHOD OF MANUFACTURING FAN-OUT PACKAGING DEVICE AND FAN-OUT PACKAGING DEVICE MANUFACTURED THEREBY |
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