VERTICAL MEMORY DEVICES INCLUDING DIVISION PATTERNS

A semiconductor device includes gate electrode structures, a first division pattern, a second division pattern, and a memory channel structure. Each gate electrode structure includes gate electrodes spaced apart from each other on a substrate in a first direction substantially perpendicular to an upper surface of the substrate. Each gate electrode extends in a second direction substantially parallel to the upper surface of the substrate. The gate electrode structures are spaced apart from each other in a third direction substantially parallel to the upper surface and crossing the second direction. The first division pattern extends in the second direction between the gate electrode structures on the substrate. The second division pattern extends in the third direction on the substrate, and is on sidewalls of end portions in the second direction of the gate electrode structures. The memory channel structure extends in the first direction through each gate electrode structure.