ENHANCED SERIAL PERIPHERAL INTERFACE

A bus system, including a clock line, a first data line, and a second data line. The bus system further includes an initiator connected to a first end of the clock line, the first data line, and the second data line. The initiator sends a start indication on the clock line and the first data line, sends command bits followed by address bits on the first data line, and sends a stop indication on the clock line and the first data line. The bus system also includes a target connected to a second end of the clock line, the first data line, and the second data line. The target sends target acknowledge information followed by target interrupt information on the second line while the command bits and address bits are sent.