MOLDED COMPOUND PATTERNS ON PACKAGE BALL SIDE TO MITIGATE COPLANARITY AND WARPAGE

Implementations described herein relate to various semiconductor device assemblies. In some implementations, a semiconductor device assembly includes a circuit substrate comprising a first substrate surface and a second substrate surface arranged opposite to the first substrate surface; at least one die arranged on the first substrate surface; a package casing disposed over the first substrate surface, wherein the package casing encapsulates the at least one die and covers at least part of the first substrate surface; a plurality of conductive interconnect structures coupled to the second substrate surface, wherein the plurality of conductive interconnect structures are electrically coupled to the at least one die via the circuit substrate; and at least one molded compound structure arranged on the second substrate surface, wherein the at least one molded compound structure is configured to reduce a coplanarity of the plurality of conductive interconnect structures.