Method And Device For Generating Integrated Circuit Layout

A method and a device for generating an integrated circuit layout are provided. The method includes: acquiring feature information corresponding to multiple components in a first layout, and determining multiple components as target components respectively, the feature information at least includes a type, a size, a layer, and a position of each component; generating default patterns corresponding to the target components based on types of the target components; generating a featureless layout by using the feature information corresponding to the target components as parameter information of the default patterns; acquiring a process rule; based on the process rule, adjusting the parameter information of the default patterns to obtain an adjusted featureless layout; and obtaining a second layout, based on the adjusted featureless layout and the process rule.