LOCATION AWARE TIMING ANALYSIS OF A DIGITAL INTEGRATED CIRCUIT

Timing analysis of a digital integrated circuit includes determining an initial delay value for a gate of an integrated circuit design. The gate is located within a predefined area of the integrated circuit design. A first scale factor is calculated based on a number of switching transistors within the predefined area, and a second scale factor is calculated based on a voltage drop value associated with the predefined area. An updated delay value for the gate is calculated based on the initial delay value, the first scale factor, and the second scale factor.