DEVICE LAYOUT DESIGN FOR IMPROVING DEVICE PERFORMANCE

The present disclosure relates an integrated chip. The integrated chip includes an isolation region disposed within a substrate and surrounding an active area. A gate structure is disposed over the substrate and has a base region and a gate extension finger protruding outward from a sidewall of the base region along a first direction to past opposing sides of the active area. A source contact and a drain contact are disposed within the active area. The drain contact is separated from the source contact by the gate extension finger. A first plurality of conductive contacts are arranged on the gate structure. The first plurality of conductive contacts are separated along the first direction by distances overlying the gate extension finger.