Techniques For Testing Input And Output Buffer Circuits Using A Test Bus

Techniques For Testing Input And Output Buffer Circuits Using A Test Bus

An integrated circuit includes first and second pads, a buffer circuit coupled to the first pad, a first pass gate circuit coupled to the first pad and to the buffer circuit, a second pass gate circuit coupled to the second pad, and a test bus coupled to the first pass gate circuit and the second pa...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: Voon, Sean Woei, Voon, Wee Sun, Bong, Pai Ho, Lim, Ching Sia
Format: Patent
Sprache:eng
Schlagworte:
BASIC ELECTRONIC CIRCUITRY
ELECTRICITY
MEASURING
MEASURING ELECTRIC VARIABLES
MEASURING MAGNETIC VARIABLES
PHYSICS
PULSE TECHNIQUE
TESTING
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Beschreibung
Zusammenfassung:An integrated circuit includes first and second pads, a buffer circuit coupled to the first pad, a first pass gate circuit coupled to the first pad and to the buffer circuit, a second pass gate circuit coupled to the second pad, and a test bus coupled to the first pass gate circuit and the second pass gate circuit. The first pass gate circuit and the second pass gate circuit are configurable to couple the second pad to the buffer circuit through the test bus during a test of the buffer circuit that is performed using the second pad.