CACHE DEVICE AND OPERATION METHOD THEREOF

The disclosure provides a cache device, which includes: a first transistor having a control terminal, a first terminal, and a second terminal, in which the first terminal of the first transistor is coupled to an input voltage, and the second terminal of the first transistor is coupled to a storage node; an inverter having an input terminal and an output terminal, in which the input terminal is coupled to the storage node; and a second transistor having a control terminal, a first terminal, and a second terminal, in which the first terminal of the second transistor is coupled to the output terminal of the inverter, and the second terminal of the second transistor is configured to output a read voltage.