SYSTEM CACHE ARCHITECTURE FOR SUPPORTING MULTIPROCESSOR ARCHITECTURE, AND CHIP

A system cache architecture for supporting a multiprocessor architecture includes: a snooping pipeline switch, at least two cache segments, a memory request arbiter and a coherent interconnect snooping requester. The snooping pipeline switch is connected to a last level memory bus of at least two processors of the multiprocessor architecture, and forwards a memory read or write request from any processor to a memory system by means of the memory request arbiter or sends the memory read or write request to any one of the at least two cache segments; the coherent interconnect snooping requester sends a snooping read or write request from a DMA master to any two cache segment; the at least two cache segments are configured to in response to concurrent read or write requests from the snooping pipeline switch or from the coherent interconnect snooping requester, feed back or update stored cached data.