FERROELECTRIC MEMORY DEVICE WITH MULTI-LEVEL BIT CELL

A ferroelectric memory device includes a substrate including a source region and a drain region, and a gate structure disposed over the substrate. The gate structure includes a gate electrode including a plurality of electrode portions arranged in a first direction parallel to a top surface of the substrate, an oxide layer including a plurality of oxide portions corresponding respectively to the plurality of electrode portions, and a ferroelectric layer disposed between the gate electrode and the oxide layer along a second direction perpendicular to the first direction and including a plurality of ferroelectric portions corresponding respectively to the plurality of oxide portions. A least one of the plurality of oxide portions and at least one of the plurality of ferroelectric portions have different thicknesses along the second direction.