Embedded-Oriented Configurable Many-Core Processor

An embedded-oriented configurable many-core processor is disclosed, which includes: an on-chip data-bus system, an on-chip event-bus system, a data connection line, a routing unit and a core. The on-chip data-bus system includes multiple transverse data-bus and vertical data-bus. The multiple transverse data-bus and vertical data-bus are staggered transversely and vertically to form N intersections, each intersection of the N intersections is correspondingly provided with a routing unit, and adjacent routing units are connected by transverse data-bus or vertical data-bus. The on-chip event-bus system includes: an event control unit, an event bus and an event signal line. Each event control unit is connected with the event bus, and is connected with the corresponding core and routing unit through the event signal line.