INTEGRATED CIRCUIT DEVICE AND METHOD OF MANUFACTURING

INTEGRATED CIRCUIT DEVICE AND METHOD OF MANUFACTURING

An integrated circuit (IC) device includes a bottom semiconductor device, a top semiconductor device over the bottom semiconductor device in a thickness direction of the IC device, and a multilayer structure between the bottom semiconductor device and the top semiconductor device in the thickness di...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: LIN, Wei-Cheng, LU, Lee-Chung, HUANG, Ching-Yu, HOU, Yung-Chin, CHENG, Yi-Kan, TZENG, Jiann-Tyng, LIN, Chun-Yen
Format: Patent
Sprache:eng
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator LIN, Wei-Cheng
LU, Lee-Chung
HUANG, Ching-Yu
HOU, Yung-Chin
CHENG, Yi-Kan
TZENG, Jiann-Tyng
LIN, Chun-Yen
description An integrated circuit (IC) device includes a bottom semiconductor device, a top semiconductor device over the bottom semiconductor device in a thickness direction of the IC device, and a multilayer structure between the bottom semiconductor device and the top semiconductor device in the thickness direction. The multilayer structure includes a lower dielectric layer over the bottom semiconductor device, an upper dielectric layer over the lower dielectric layer, and an interlayer metal structure between the lower dielectric layer and the upper dielectric layer. The interlayer metal structure is electrically coupled to at least one of the bottom semiconductor device or the top semiconductor device.
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2024274585A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2024274585A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2024274585A13</originalsourceid><addsrcrecordid>eNrjZDD19AtxdQ9yDHF1UXD2DHIO9QxRcHEN83R2VXD0c1HwdQ3x8HdR8HdT8HX0C3VzdA4JDfL0c-dhYE1LzClO5YXS3AzKbq4hzh66qQX58anFBYnJqXmpJfGhwUYGRiZG5iamFqaOhsbEqQIAfr8ohQ</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>INTEGRATED CIRCUIT DEVICE AND METHOD OF MANUFACTURING</title><source>esp@cenet</source><creator>LIN, Wei-Cheng ; LU, Lee-Chung ; HUANG, Ching-Yu ; HOU, Yung-Chin ; CHENG, Yi-Kan ; TZENG, Jiann-Tyng ; LIN, Chun-Yen</creator><creatorcontrib>LIN, Wei-Cheng ; LU, Lee-Chung ; HUANG, Ching-Yu ; HOU, Yung-Chin ; CHENG, Yi-Kan ; TZENG, Jiann-Tyng ; LIN, Chun-Yen</creatorcontrib><description>An integrated circuit (IC) device includes a bottom semiconductor device, a top semiconductor device over the bottom semiconductor device in a thickness direction of the IC device, and a multilayer structure between the bottom semiconductor device and the top semiconductor device in the thickness direction. The multilayer structure includes a lower dielectric layer over the bottom semiconductor device, an upper dielectric layer over the lower dielectric layer, and an interlayer metal structure between the lower dielectric layer and the upper dielectric layer. The interlayer metal structure is electrically coupled to at least one of the bottom semiconductor device or the top semiconductor device.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2024</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20240815&amp;DB=EPODOC&amp;CC=US&amp;NR=2024274585A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,777,882,25545,76296</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20240815&amp;DB=EPODOC&amp;CC=US&amp;NR=2024274585A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>LIN, Wei-Cheng</creatorcontrib><creatorcontrib>LU, Lee-Chung</creatorcontrib><creatorcontrib>HUANG, Ching-Yu</creatorcontrib><creatorcontrib>HOU, Yung-Chin</creatorcontrib><creatorcontrib>CHENG, Yi-Kan</creatorcontrib><creatorcontrib>TZENG, Jiann-Tyng</creatorcontrib><creatorcontrib>LIN, Chun-Yen</creatorcontrib><title>INTEGRATED CIRCUIT DEVICE AND METHOD OF MANUFACTURING</title><description>An integrated circuit (IC) device includes a bottom semiconductor device, a top semiconductor device over the bottom semiconductor device in a thickness direction of the IC device, and a multilayer structure between the bottom semiconductor device and the top semiconductor device in the thickness direction. The multilayer structure includes a lower dielectric layer over the bottom semiconductor device, an upper dielectric layer over the lower dielectric layer, and an interlayer metal structure between the lower dielectric layer and the upper dielectric layer. The interlayer metal structure is electrically coupled to at least one of the bottom semiconductor device or the top semiconductor device.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2024</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZDD19AtxdQ9yDHF1UXD2DHIO9QxRcHEN83R2VXD0c1HwdQ3x8HdR8HdT8HX0C3VzdA4JDfL0c-dhYE1LzClO5YXS3AzKbq4hzh66qQX58anFBYnJqXmpJfGhwUYGRiZG5iamFqaOhsbEqQIAfr8ohQ</recordid><startdate>20240815</startdate><enddate>20240815</enddate><creator>LIN, Wei-Cheng</creator><creator>LU, Lee-Chung</creator><creator>HUANG, Ching-Yu</creator><creator>HOU, Yung-Chin</creator><creator>CHENG, Yi-Kan</creator><creator>TZENG, Jiann-Tyng</creator><creator>LIN, Chun-Yen</creator><scope>EVB</scope></search><sort><creationdate>20240815</creationdate><title>INTEGRATED CIRCUIT DEVICE AND METHOD OF MANUFACTURING</title><author>LIN, Wei-Cheng ; LU, Lee-Chung ; HUANG, Ching-Yu ; HOU, Yung-Chin ; CHENG, Yi-Kan ; TZENG, Jiann-Tyng ; LIN, Chun-Yen</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2024274585A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2024</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>LIN, Wei-Cheng</creatorcontrib><creatorcontrib>LU, Lee-Chung</creatorcontrib><creatorcontrib>HUANG, Ching-Yu</creatorcontrib><creatorcontrib>HOU, Yung-Chin</creatorcontrib><creatorcontrib>CHENG, Yi-Kan</creatorcontrib><creatorcontrib>TZENG, Jiann-Tyng</creatorcontrib><creatorcontrib>LIN, Chun-Yen</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>LIN, Wei-Cheng</au><au>LU, Lee-Chung</au><au>HUANG, Ching-Yu</au><au>HOU, Yung-Chin</au><au>CHENG, Yi-Kan</au><au>TZENG, Jiann-Tyng</au><au>LIN, Chun-Yen</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>INTEGRATED CIRCUIT DEVICE AND METHOD OF MANUFACTURING</title><date>2024-08-15</date><risdate>2024</risdate><abstract>An integrated circuit (IC) device includes a bottom semiconductor device, a top semiconductor device over the bottom semiconductor device in a thickness direction of the IC device, and a multilayer structure between the bottom semiconductor device and the top semiconductor device in the thickness direction. The multilayer structure includes a lower dielectric layer over the bottom semiconductor device, an upper dielectric layer over the lower dielectric layer, and an interlayer metal structure between the lower dielectric layer and the upper dielectric layer. The interlayer metal structure is electrically coupled to at least one of the bottom semiconductor device or the top semiconductor device.</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng
recordid cdi_epo_espacenet_US2024274585A1
source esp@cenet
subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title INTEGRATED CIRCUIT DEVICE AND METHOD OF MANUFACTURING
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-17T16%3A25%3A33IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=LIN,%20Wei-Cheng&rft.date=2024-08-15&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS2024274585A1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true