SEMICONDUCTOR STRUCTURE WITH ENHANCED VOLTAGE STRESS CONTROL AND METHOD OF FORMING THE SAME

A method includes: accessing a first cell, where the first cell includes: a first active region and a second active; gate electrodes arranged in a second layer over the first layer; first conductive lines extending in the second layer; second conductive lines extending in the second layer; a third and a fourth conductive lines extending in a third layer over the second layer; and first gate vias arranged in a fourth layer and electrically coupled to the gate electrodes. The method also includes: determining a performance metric and a dielectric voltage stress level; and in response to the performance metric or the dielectric voltage stress level failing to fulfilling a specification, revising the first cell to generate a second cell by moving at least one of the first gate vias to be electrically coupled to the fourth conductive line.