3D MEMORY CELLS AND ARRAY ARCHITECTURES

Various 3D memory cells, array architectures, and processes are disclosed. In an embodiment, a cell structure includes a bit line, source line, front gate, and back gate. The cell structure also includes a floating body having surfaces coupled to the bit line, source line, front gate, and back gate. The floating body has a selected thickness between the front gate and the back gate. When the cell is in a data 0 state and selected voltages are supplied to the bit line, the source line, and the front gate and a negative voltage is supplied to the back gate, channel current between the bit line and the source line flows at a first level. When the cell is in a data 1 state, the channel current between the bit line and the source line flows at a second level to provide an enlarged current sensing window.