Integrated Circuitry, Memory Circuitry Comprising Strings Of Memory Cells, And Methods Used In Forming Integrated Circuitry

A method used in forming integrated circuitry comprises forming a stack comprising vertically-alternating first tiers and second tiers of different compositions relative one another. The stack extends from individual die areas to and across scribe-line area that is between immediately-adjacent of the individual die areas. A registration mark is formed in the scribe-line area. The registration mark comprises parallel first bars atop the stack having first spaces therebetween. A masking material is directly above the stack, the first bars, and the first spaces. The masking material comprises parallel second bars having second spaces therebetween. The second spaces individually have width that is less than width of individual of the second bars. Some of the masking material is spaced laterally-outward of the second bars. Vertical thickness of the some masking material that is laterally-outward of the second bars have a vertical thickness laterally-outward of the first spaces that is greater than vertical thickness of the second bars. Ratio of the vertical thickness of the some masking material that is laterally-outward of the second bars divided by the width of the second bars is 6.0 to 9.6. After forming the registration mark, the first bars and the first and second tiers in the scribe-line area are cut through to form individual die that individually comprise one of the individual die areas. Other embodiments, including structure independent of method, are disclosed.