BUFFER CHIP, AND SEMICONDUCTOR PACKAGE INCLUDING BUFFER CHIP AND MEMORY CHIP

A buffer chip includes a control signal transmission path that transmitting, to a memory chip, control signals transmitted from a memory controller; a data transmission path including a variable delay circuit having a delay value adjusted by a delay code and transmitting, to the memory controller, data transmitted from the memory chip; a ring oscillator generating a ring oscillator clock; a counter circuit configured to count the number of toggles of the ring oscillator clock while an external clock toggles a reference number of times; a reference value storage circuit configured to store a counting value of the counter circuit as a reference value; a current value storage circuit configured to store the counting value of the counter circuit as a current value in response to a comparison signal; and a code generation circuit configured to generate the delay code by comparing the reference value with the current value.