STACKED CHIP SCALE SEMICONDUCTOR DEVICE

A stacked chip scale semiconductor device includes one or more semiconductor die stacks. Each semiconductor die stack may include a pair of semiconductor dies. A first of the pair of semiconductor dies may be provided with a pattern of contact pads distributed across its major surface configured to be flip chip bonded to a host device. A second of the pair of semiconductor dies may include a row of contact pads. The first semiconductor die may be bonded on top of the second semiconductor die in an offset, stepped configuration so that the row of contact pads of the second semiconductor die is left exposed. Like channels of contact pads on the first and second semiconductor dies may then be electrically coupled by additive manufacturing or conductive trace printing.