Integrated Circuitry, Memory Circuitry Comprising Strings Of Memory Cells, And Methods Used In Forming Integrated Circuitry

A method used in forming integrated circuitry comprises forming a stack comprising vertically-alternating first tiers and second tiers. The first tiers comprise sacrificial material and the second tiers comprise non-sacrificial material that is of different composition from that of the sacrificial material. The stack extends from individual die areas to and across scribe-line area that is between immediately-adjacent of the individual die areas. The scribe-line area comprises a horizontal area in which a registration mark or an alignment mark is being fabricated. Horizontally-spaced features of the registration mark or of the alignment mark are simultaneously formed in the first tiers and the second tiers in the horizontal area and in the individual die areas. The horizontally-spaced features in the horizontal area are grouped in sections that are horizontally-separated by gaps in at least one vertical cross-section where there are less, if any, such horizontally-spaced features than are in the sections. Horizontally-spaced vertical slots are formed through uppermost of the first and second tiers of the stack in the horizontal area of the registration mark or of the alignment mark. Through the horizontally-spaced vertical slots, the sacrificial material is replaced with metal material. After the replacing, the first and second tiers in the scribe-line areas are cut through to form individual die that individually comprise one of the individual die areas. Other embodiments, including structure, are disclosed.