MEMORY DEVICE REDUCING I/O SIGNAL LINES THROUGH I/O MAPPING CONNECTION AND MEMORY SYSTEM INCLUDING THE SAME

Disclosed is a memory system including a memory device and a memory controller. The memory device includes a package of a first memory chip configured to receive input/output signals through first input/output pads and a second memory chip having second input/output pads connected to the first input/output pads by a mapping connection. The memory controller configured to provide the input/output signals to the memory device. The second memory chip is configured to receive input/output signals different from the input/output signals provided by the memory controller to the first memory chip due to the mapping connection. The first and second memory chips are configured to selectively ignore the input/output signals provided by the memory controller based on the mapping connection.