SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE

Semiconductor package includes lower redistribution layer providing first redistribution wirings and having first region and second region surrounding the first region, semiconductor chip disposed on the first region and electrically connected to the first redistribution wirings, sealing member cove...

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Bibliographische Detailangaben
Hauptverfasser: Kim, Wooyoung, Cho, Bongju, Lee, Sangkyu, Kim, Jingu, Kwon, Yieok, Lee, Gongje
Format: Patent
Sprache:eng
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Zusammenfassung:Semiconductor package includes lower redistribution layer providing first redistribution wirings and having first region and second region surrounding the first region, semiconductor chip disposed on the first region and electrically connected to the first redistribution wirings, sealing member covering the semiconductor chip on the lower redistribution layer, plurality of vertical conductive structures penetrating the sealing member on the second region and electrically connected to the first redistribution wirings, upper redistribution layer disposed on the sealing member and having second redistribution wirings electrically connected to the plurality of vertical conductive structures and plurality of bonding pads. The vertical conductive structures are bonded to the bonding pad and extend vertically from the plurality of bonding pads. The vertical conductive structure includes first to third conductive pillar portions sequentially stacked. The first conductive pillar portion has first length and the third conductive pillar portion has third length greater than the first length.