Leveraging System Cache for Performance Cores
Methods and apparatus relating to leveraging system cache for performance cores are described. In an embodiment, a system cache stores one or more cachelines that are to be evicted from a processor cache. Logic circuitry determines whether to store the one or more cachelines in the system cache base...
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| Format: | Patent |
| Sprache: | eng |
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| Zusammenfassung: | Methods and apparatus relating to leveraging system cache for performance cores are described. In an embodiment, a system cache stores one or more cachelines that are to be evicted from a processor cache. Logic circuitry determines whether to store the one or more cachelines in the system cache based at least in part on comparison of a threshold value with a hit rate associated with the one or more cachelines. Other embodiments are also disclosed and claimed. |
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