RESTRICTING VECTOR LENGTH IN A PROCESSOR

Techniques to restrict vector length in a processor are described. A method of an aspect that may be performed by a processor includes executing first instances of vector instructions having respective opcode values regardless of whether they specify wider vectors of a wider vector width or narrower vectors of a narrower vector width, when a control value is a first value. The method also includes executing second instances of vector instructions having the respective opcode values when they specify narrower vectors of the narrower vector width, but do not specify wider vectors of the wider vector width, when the control value is a second different value. The method also includes preventing execution of third instances of vector instructions having the respective opcode values when they specify wider vectors of the wider vector width, when the control value is the second value. Other methods, processors, and systems are disclosed.