APPARATUS AND METHOD FOR PROBABILISTIC CACHE REPLACEMENT FOR ACCELERATING ADDRESS TRANSLATION

Apparatus and method for probabilistic cacheline replacement for accelerating address translation. For example, one embodiment of a processor comprises: a plurality of cores, each core to process instructions; a cache to be shared by a subset of the plurality of cores, the cache comprising an N-way...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	RAKSHIT, JOYDEEP, SUBRAMONEY, SREENIVAS, NORI, ANANT VITHAL, ALAM, HANNA, NUZMAN, JOSEPH
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
Online-Zugang:	Volltext bestellen
Tags:	Tag hinzufügen Keine Tags, Fügen Sie den ersten Tag hinzu!