APPARATUS AND METHOD FOR PROBABILISTIC CACHE REPLACEMENT FOR ACCELERATING ADDRESS TRANSLATION

APPARATUS AND METHOD FOR PROBABILISTIC CACHE REPLACEMENT FOR ACCELERATING ADDRESS TRANSLATION

Apparatus and method for probabilistic cacheline replacement for accelerating address translation. For example, one embodiment of a processor comprises: a plurality of cores, each core to process instructions; a cache to be shared by a subset of the plurality of cores, the cache comprising an N-way...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: RAKSHIT, JOYDEEP, SUBRAMONEY, SREENIVAS, NORI, ANANT VITHAL, ALAM, HANNA, NUZMAN, JOSEPH
Format: Patent
Sprache:eng
Schlagworte:
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Beschreibung
Zusammenfassung:Apparatus and method for probabilistic cacheline replacement for accelerating address translation. For example, one embodiment of a processor comprises: a plurality of cores, each core to process instructions; a cache to be shared by a subset of the plurality of cores, the cache comprising an N-way set associative cache for storing page table entry (PTE) cachelines and non-PTE cachelines; and a cache manager to implement a PTE-aware eviction policy for evicting cachelines from the cache, the PTE-aware eviction policy to cause a reduction of evictions of PTE cachelines during non-PTE cacheline fills.