SIDEBAND INSTRUCTION ADDRESS TRANSLATION

Embodiments relate to sideband instruction address translation. According to an aspect, a computer-implemented method includes managing, within a processor, an instruction effective-to-real-address table (I-ERAT) separate from a main ERAT, where the I-ERAT has a smaller storage capacity than the main ERAT. The method also includes indicating an I-ERAT hit based on determining that an instruction address for an instruction cache is stored in the I-ERAT, bypassing an arbitrator within the processor and sending a translated address from the I-ERAT to the instruction cache based on detecting the I-ERAT hit, and sending an address translation request through the arbitrator to the main ERAT based on an I-ERAT miss and writing a translation result of the main ERAT to the I-ERAT.