MEMORY DEVICE AND OPERATING METHOD THEREOF

A memory device is provided. The memory device includes: memory cells respectively connected with word lines; first ground selection transistors connected with a first ground selection line programmed to have a first threshold voltage; second ground selection transistors connected with a second ground selection line programmed to have a second threshold voltage which differs from the first threshold voltage; and a control circuit configured to: control an erase operation to be performed on each of at least one first ground selection transistor of the first ground selection transistors based on a threshold voltage of each of the at least one first ground selection transistor being greater than a predetermined first criterion; and control a threshold voltage of each of the second ground selection transistors to be compared with a predetermined second criterion based on the erase operation on the at least one first ground selection transistor being completed.