THREE-DIMENSIONAL MEMORY DEVICE AND FABRICATION METHOD FOR IMPROVED YIELD AND RELIABILITY
A 3D memory device includes a conductor/insulator stack containing a conductive layer and a dielectric layer alternatingly stacked, channel hole structures in a first region of memory cells in the conductor/insulator stack, a blocking structure adjacent to the first region, and a dummy channel hole...
Gespeichert in:
Hauptverfasser: | , , , , , , |
---|---|
Format: | Patent |
Sprache: | eng |
Schlagworte: | |
Online-Zugang: | Volltext bestellen |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
container_end_page | |
---|---|
container_issue | |
container_start_page | |
container_title | |
container_volume | |
creator | HUO, Zongliang WU, Linchun HAN, Yuhui ZHANG, Kun XIA, Zhiliang ZHOU, Wenxi SUN, Changzhi |
description | A 3D memory device includes a conductor/insulator stack containing a conductive layer and a dielectric layer alternatingly stacked, channel hole structures in a first region of memory cells in the conductor/insulator stack, a blocking structure adjacent to the first region, and a dummy channel hole structure in the first region. The dummy channel hole structure is adjacent to the blocking structure, and includes a dielectric material that fills a channel hole to form a first dielectric filling structure. |
format | Patent |
fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2024179901A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2024179901A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2024179901A13</originalsourceid><addsrcrecordid>eNqNiksKwjAUALtxIeodAq4LTRWkyzR5JQ_ykde0kFUpEleihXp_DOIBXA3MzLaIQRNAqdCC69E7YZgF6ykyBSNKYMIp1omWUIqQe65B-6w8MbRX8iMoFhGM-p4EBkWLBkPcF5v7_FjT4cddcewgSF2m5TWldZlv6Zne09DXVX3ml6apuOCn_64P3vAyYg</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>THREE-DIMENSIONAL MEMORY DEVICE AND FABRICATION METHOD FOR IMPROVED YIELD AND RELIABILITY</title><source>esp@cenet</source><creator>HUO, Zongliang ; WU, Linchun ; HAN, Yuhui ; ZHANG, Kun ; XIA, Zhiliang ; ZHOU, Wenxi ; SUN, Changzhi</creator><creatorcontrib>HUO, Zongliang ; WU, Linchun ; HAN, Yuhui ; ZHANG, Kun ; XIA, Zhiliang ; ZHOU, Wenxi ; SUN, Changzhi</creatorcontrib><description>A 3D memory device includes a conductor/insulator stack containing a conductive layer and a dielectric layer alternatingly stacked, channel hole structures in a first region of memory cells in the conductor/insulator stack, a blocking structure adjacent to the first region, and a dummy channel hole structure in the first region. The dummy channel hole structure is adjacent to the blocking structure, and includes a dielectric material that fills a channel hole to form a first dielectric filling structure.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2024</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20240530&DB=EPODOC&CC=US&NR=2024179901A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20240530&DB=EPODOC&CC=US&NR=2024179901A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>HUO, Zongliang</creatorcontrib><creatorcontrib>WU, Linchun</creatorcontrib><creatorcontrib>HAN, Yuhui</creatorcontrib><creatorcontrib>ZHANG, Kun</creatorcontrib><creatorcontrib>XIA, Zhiliang</creatorcontrib><creatorcontrib>ZHOU, Wenxi</creatorcontrib><creatorcontrib>SUN, Changzhi</creatorcontrib><title>THREE-DIMENSIONAL MEMORY DEVICE AND FABRICATION METHOD FOR IMPROVED YIELD AND RELIABILITY</title><description>A 3D memory device includes a conductor/insulator stack containing a conductive layer and a dielectric layer alternatingly stacked, channel hole structures in a first region of memory cells in the conductor/insulator stack, a blocking structure adjacent to the first region, and a dummy channel hole structure in the first region. The dummy channel hole structure is adjacent to the blocking structure, and includes a dielectric material that fills a channel hole to form a first dielectric filling structure.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2024</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNiksKwjAUALtxIeodAq4LTRWkyzR5JQ_ykde0kFUpEleihXp_DOIBXA3MzLaIQRNAqdCC69E7YZgF6ykyBSNKYMIp1omWUIqQe65B-6w8MbRX8iMoFhGM-p4EBkWLBkPcF5v7_FjT4cddcewgSF2m5TWldZlv6Zne09DXVX3ml6apuOCn_64P3vAyYg</recordid><startdate>20240530</startdate><enddate>20240530</enddate><creator>HUO, Zongliang</creator><creator>WU, Linchun</creator><creator>HAN, Yuhui</creator><creator>ZHANG, Kun</creator><creator>XIA, Zhiliang</creator><creator>ZHOU, Wenxi</creator><creator>SUN, Changzhi</creator><scope>EVB</scope></search><sort><creationdate>20240530</creationdate><title>THREE-DIMENSIONAL MEMORY DEVICE AND FABRICATION METHOD FOR IMPROVED YIELD AND RELIABILITY</title><author>HUO, Zongliang ; WU, Linchun ; HAN, Yuhui ; ZHANG, Kun ; XIA, Zhiliang ; ZHOU, Wenxi ; SUN, Changzhi</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2024179901A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2024</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>HUO, Zongliang</creatorcontrib><creatorcontrib>WU, Linchun</creatorcontrib><creatorcontrib>HAN, Yuhui</creatorcontrib><creatorcontrib>ZHANG, Kun</creatorcontrib><creatorcontrib>XIA, Zhiliang</creatorcontrib><creatorcontrib>ZHOU, Wenxi</creatorcontrib><creatorcontrib>SUN, Changzhi</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>HUO, Zongliang</au><au>WU, Linchun</au><au>HAN, Yuhui</au><au>ZHANG, Kun</au><au>XIA, Zhiliang</au><au>ZHOU, Wenxi</au><au>SUN, Changzhi</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>THREE-DIMENSIONAL MEMORY DEVICE AND FABRICATION METHOD FOR IMPROVED YIELD AND RELIABILITY</title><date>2024-05-30</date><risdate>2024</risdate><abstract>A 3D memory device includes a conductor/insulator stack containing a conductive layer and a dielectric layer alternatingly stacked, channel hole structures in a first region of memory cells in the conductor/insulator stack, a blocking structure adjacent to the first region, and a dummy channel hole structure in the first region. The dummy channel hole structure is adjacent to the blocking structure, and includes a dielectric material that fills a channel hole to form a first dielectric filling structure.</abstract><oa>free_for_read</oa></addata></record> |
fulltext | fulltext_linktorsrc |
identifier | |
ispartof | |
issn | |
language | eng |
recordid | cdi_epo_espacenet_US2024179901A1 |
source | esp@cenet |
subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
title | THREE-DIMENSIONAL MEMORY DEVICE AND FABRICATION METHOD FOR IMPROVED YIELD AND RELIABILITY |
url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-04T07%3A56%3A56IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=HUO,%20Zongliang&rft.date=2024-05-30&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS2024179901A1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |