CHIP PACKAGE STRUCTURE AND PACKAGING METHOD THEREOF, AND ELECTRONIC DEVICE
A chip package structure includes: a substrate, a first connection chip, conductive columns, a first packaging layer, a first chip, and a second chip. The first connection chip is disposed on the substrate. The conductive columns is disposed on the substrate and located on a periphery of the first c...
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Format: | Patent |
Sprache: | eng |
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Zusammenfassung: | A chip package structure includes: a substrate, a first connection chip, conductive columns, a first packaging layer, a first chip, and a second chip. The first connection chip is disposed on the substrate. The conductive columns is disposed on the substrate and located on a periphery of the first connection chip. The first packaging layer is disposed on the substrate and wrapping the first connection chip and the conductive columns, with the active surface of the first connection chip and top surfaces of the conductive columns exposed. The first chip is disposed on the first packaging layer, and coupled to both the conductive columns and the first connection chip. The second chip is disposed on the first packaging layer and that is away from the substrate, and coupled to both the conductive columns and the first connection chip. |
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