SEMICONDUCTOR PACKAGE

A semiconductor package, including a first redistribution substrate, a semiconductor chip on the first redistribution substrate, a connection structure on the first redistribution substrate and spaced apart from the semiconductor chip, the connection structure including a connection substrate and a post on the connection substrate, a second redistribution substrate on the semiconductor chip and the connection structure, and a molding layer between the first redistribution substrate and the second redistribution substrate, the molding layer encapsulating the semiconductor chip and the connection structure, wherein the connection substrate includes a conductive pattern that vertically penetrates the connection substrate, the post is in contact with a top surface of the conductive pattern, and a width of the post is less than a width of the connection substrate.