STACKED 3D CACHE CONFIGURATION WITH ON-CHIP POWER SUPPORT

A semiconductor module includes a first semiconductor die, which comprises (i) a power support structure and (ii) a first cache region; and a second semiconductor die, which is mounted on top of the first semiconductor die and comprises (i) a logic core, which overlies and is electrically connected...

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Bibliographische Detailangaben
Hauptverfasser: Golz, John W, Rubin, Joshua M, Kumar, Arvind, Takken, Todd Edward
Format: Patent
Sprache:eng
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Beschreibung
Zusammenfassung:A semiconductor module includes a first semiconductor die, which comprises (i) a power support structure and (ii) a first cache region; and a second semiconductor die, which is mounted on top of the first semiconductor die and comprises (i) a logic core, which overlies and is electrically connected to the power support structure, and (ii) a second cache region, which overlies and is electrically connected to the first cache region.