SYSTEMS AND METHODS FOR REDUCING ERROR LOG REQUIRED SPACE IN SEMICONDUCTOR TESTING

A memory testing device uses a master control unit (MCU) to concurrently operate multiple, intelligent, slave control units (SCUs). The MCU or an SCU translates memory addresses of a device under test (DUT) into a matrix. The SCU accumulates error data by testing a test bit of the memory across multiple cells of the matrix, the accumulated error data is post-processed to determine if the test bit is faulty, and the process is repeated for additional test bits. The post-processed data is analyzed to identify one or more of the test bits as faulty, and then include in a test log preferably only a single instance of a memory address that corresponds to each of the one or more faulty test bits.