SEMICONDUCTOR MEMORY DEVICES

A semiconductor memory device including a semiconductor layer including a source area, a channel area, and a drain area arranged in a first horizontal direction on a substrate, a cell capacitor extending in the first horizontal direction on the substrate and including a lower electrode layer, a capacitor dielectric film, and an upper electrode layer connected to the source area, a bit line extending in a vertical direction on the substrate and connected to the drain area, and a gate structure covering the channel area, and the gate structure including a gate dielectric film on the channel area and a gate electrode film on the gate dielectric film, wherein in the vertical direction, a first thickness of an end of the channel area facing the source area is greater than a second thickness of another end of the channel area facing the drain area may be provided.