DIELECTRIC ISOLATION LAYER BETWEEN A NANOWIRE TRANSISTOR AND A SUBSTRATE

DIELECTRIC ISOLATION LAYER BETWEEN A NANOWIRE TRANSISTOR AND A SUBSTRATE

Gate all around semiconductor devices, such as nanowire or nanoribbon devices, are described that include a low dielectric constant ("low-k") material disposed between a first nanowire closest to the substrate and the substrate. This configuration enables gate control over all surfaces of...

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Bibliographische Detailangaben
Hauptverfasser: KANG, Jun Sung, GULER, Leonard, GUHA, Biswajeet, HSU, William, BEATTIE, Bruce E
Format: Patent
Sprache:eng
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Beschreibung
Zusammenfassung:Gate all around semiconductor devices, such as nanowire or nanoribbon devices, are described that include a low dielectric constant ("low-k") material disposed between a first nanowire closest to the substrate and the substrate. This configuration enables gate control over all surfaces of the nanowires in a channel region of a semiconductor device via the high-k dielectric material, while also preventing leakage current from the first nanowire into the substrate.