CELL ARCHITECTURE WITH CENTER-LINE POWER RAILS FOR STACKED FIELD-EFFECT TRANSISTORS

A cell architecture including at least one semiconductor device cell is provided. The cell includes: a 1st active pattern and a 2nd active pattern extended in a 1st direction, the 1st active pattern at least partially overlapping the 2nd active pattern in a 3rd direction intersecting the direction; a plurality of gate structures extended in a 2nd direction across the 1st and 2nd active patterns, the 2nd direction intersecting the 1st direction and the 3rd direction; a plurality of metal lines in at least one metal layer of the cell, the metal lines being extended in the 1st direction, and at least one of the metal lines being connected to at least one of the 1st and 2nd active patterns and the gate structures; and at least one power rail connecting the at least one of the 1st and 2nd active patterns to at least one voltage source, wherein the at least one power rail is disposed to be closer to a virtual horizontal center line of the cell extended in the 1st direction than an upper boundary or a lower boundary of the cell.