Multiply-Instantiated Block Modeling For Circuit Component Placement In Integrated Circuit

Aspects of the disclosure provide for eliminating or reducing uniquification of blocks in a chip-level graph of a computer chip, to reduce the size of the graph while still encoding block-specific information. For each group of blocks in the graph generated from a multiply-instantiated block (MIB),...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: Carpenter, Roger David, Sinha, Debjit, Rodman, Paul Kingsley, Lee, Young-Joon, Jin, Xuyang, Kim, Myung-Chul
Format: Patent
Sprache:eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:Aspects of the disclosure provide for eliminating or reducing uniquification of blocks in a chip-level graph of a computer chip, to reduce the size of the graph while still encoding block-specific information. For each group of blocks in the graph generated from a multiply-instantiated block (MIB), a block in the group is selected as a base block. The physical position of the base block is encoded in a reduced graph, and the physical positions of the remaining blocks are encoded as a linear transformation of the physical position of the base block across the face of the chip. Each group of blocks instantiated from the same MIB is represented as a single instance. The reduced graph can be fed into a device configured to perform a circuit component placement process, to identify the placement of circuit components for blocks in the chip in accordance with one or more objectives.