MODIFIED INTERNAL CLEARANCE(S) AT CONNECTOR PIN APERTURE(S) OF A CIRCUIT BOARD

A method of fabricating a multilayer circuit board is provided which includes forming a layer of a the multilayer circuit board with an internal clearance region having a modified voltage-to-ground clearance of conductive material adjacent to an aperture of the multilayer circuit board. The modified...

Ausführliche Beschreibung

Gespeichert in:

Bibliographische Detailangaben
Hauptverfasser:	LEWIS, Theron Lee, YOUNGER, Timothy P, BIELICK, James D, JENNINGS, Timothy, BRAUN, David J, DANGLER, John R, HUGO, Stephen Michael
Format:	Patent
Sprache:	eng
Schlagworte:	CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR ELECTRICITY MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS PRINTED CIRCUITS
Online-Zugang:	Volltext bestellen
Tags:	Tag hinzufügen Keine Tags, Fügen Sie den ersten Tag hinzu!

Beschreibung
Zusammenfassung:	A method of fabricating a multilayer circuit board is provided which includes forming a layer of a the multilayer circuit board with an internal clearance region having a modified voltage-to-ground clearance of conductive material adjacent to an aperture of the multilayer circuit board. The modified voltage-to-ground clearance of conductive material is based on a configuration of a connector pin to be press-fit connected within the aperture of the multilayer circuit board, and the internal clearance region is enlarged in a direction of greatest normal force outward from the aperture with insertion of the connector pin into the aperture.