IMPLEMENTING HETEROGENEOUS INSTRUCTION SETS IN HETEROGENEOUS COMPUTE ARCHITECTURES

IMPLEMENTING HETEROGENEOUS INSTRUCTION SETS IN HETEROGENEOUS COMPUTE ARCHITECTURES

In one embodiment, an apparatus includes a plurality of processing cores, where each processing core is capable of executing at least one of a subset of an instruction set architecture (ISA). The apparatus also includes hardware circuitry to determine, during runtime, whether a thread comprising ins...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: McDonnell, Niall, Schatzberg, Gershon, Hoban, Adrian C, Guim Bernat, Francesc, Metsch, Thijs
Format: Patent
Sprache:eng
Schlagworte:
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Beschreibung
Zusammenfassung:In one embodiment, an apparatus includes a plurality of processing cores, where each processing core is capable of executing at least one of a subset of an instruction set architecture (ISA). The apparatus also includes hardware circuitry to determine, during runtime, whether a thread comprising instructions of a particular ISA subset can execute on a particular processing core, and based on the determination, indicate a capability of the thread to be executed on the particular processing core in subsequent executions.