LOW POWER FLIP-FLOP

A low power flip-flop includes a master section including a multiplexer, a first AND-OR-Inverter (AOI) gate circuit, a second AOI gate circuit, and a first inverter circuit and configured to receive a data input signal, a scan input signal, a scan enable signal, and an inverted scan enable signal, and output a second internal signal and a third internal signal, a slave section including a third AOI gate circuit, a fourth AOI gate circuit, and a second inverter circuit, and configured to receive the second and third internal signals to output an output signal, and a third inverter circuit configured to generate the inverted scan enable signal. The first to fourth AOI gate circuits are configured to receive a clock signal.