REDUCED ESR IN TRENCH CAPACITOR

A method of fabricating an integrated circuit includes etching trenches in a first surface of a semiconductor layer. A trench dielectric layer is formed over the first surface and over bottoms and sidewalls of the trenches and a doped polysilicon layer is formed over the trench dielectric layer and...

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Bibliographische Detailangaben
Hauptverfasser:	Liu, Dongsheng, Yang, Shengpin, Hu, Jing, Zuo, Chao, Jain, Manoj K, Feng, ZHI PENG, Liu, Yunlong
Format:	Patent
Sprache:	eng
Schlagworte:	BASIC ELECTRIC ELEMENTS CAPACITORS CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES ORLIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES
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Beschreibung
Zusammenfassung:	A method of fabricating an integrated circuit includes etching trenches in a first surface of a semiconductor layer. A trench dielectric layer is formed over the first surface and over bottoms and sidewalls of the trenches and a doped polysilicon layer is formed over the trench dielectric layer and within the trenches. The doped polysilicon layer is patterned to form a polysilicon bridge that connects to the polysilicon within the filled trenches and a blanket implant of a first dopant is directed to the polysilicon bridge and to the first surface. The blanket implant forms a contact region extending from the first surface into the semiconductor layer.