OVERLAY MARK, MANUFACTURING METHOD USING THE SAME, AND SEMICONDUCTOR DEVICE USING THE SAME

Provided is an overlay mark. The overlay mark comprises a substrate, a lower overlay in the substrate, a pattern layer on the substrate, and an upper overlay defining an opening on the pattern layer. The lower overlay does not overlap the upper overlay in a thickness direction of the substrate.

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Bibliographische Detailangaben
Hauptverfasser: CHA, A Yeong, CHOI, Jung Hyun, HAN, Jong Hee, PARK, Sang Won, SON, Byeong-Hwan, LEE, Hye Jin
Format: Patent
Sprache:eng
Schlagworte:
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Beschreibung
Zusammenfassung:Provided is an overlay mark. The overlay mark comprises a substrate, a lower overlay in the substrate, a pattern layer on the substrate, and an upper overlay defining an opening on the pattern layer. The lower overlay does not overlap the upper overlay in a thickness direction of the substrate.