MEMORY DEVICE, FAILURE BITS DETECTOR AND FAILURE BITS DETECTION METHOD THEREOF

MEMORY DEVICE, FAILURE BITS DETECTOR AND FAILURE BITS DETECTION METHOD THEREOF

A memory device, a failure bits detector, and a failure bits detection method thereof are provided. The failure bits detector includes a current generator, a current mirror, and a comparator. The current generator generates a first current according to a reference code. The current mirror mirrors th...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: Wu, Chung-Han, Yang, Shang-Chi, Liang, Che-Wei, Chiang, Chih-He
Format: Patent
Sprache:eng
Schlagworte:
CONTROLLING
INFORMATION STORAGE
PHYSICS
REGULATING
STATIC STORES
SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
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Beschreibung
Zusammenfassung:A memory device, a failure bits detector, and a failure bits detection method thereof are provided. The failure bits detector includes a current generator, a current mirror, and a comparator. The current generator generates a first current according to a reference code. The current mirror mirrors the first current to generate a second current at a second end of the current mirror. The comparator compares a first voltage at a first input end with a second voltage at a second input end to generate a detection result.