Techniques for Monitoring Digital Timing Margins

Various implementations described herein are directed to a device having core circuitry and hardware with functional paths and canary paths that are co-located with the functional paths. The device may have timing monitors that monitor and measure digital timing margins of the functional paths and the canary paths during droop events. Also, the device may have a control processor that sets-up parameters for hardware droop mitigation based on the digital timing margins, wherein the control processor calibrates the hardware for droop response or for adaptive clock and power control for droop mitigation based on the digital timing margins.