BIT FLIP AWARE LATCH PLACEMENT

A method, system, and computer program product for bit flip aware latch placement in integrated circuit generation are provided. The method identifies a chip design for an integrated circuit. A set of chip design constraints, associated with the chip design, is identified. A set of checking groups,...

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Bibliographische Detailangaben
Hauptverfasser:	Trombley, Benjamin Neil, Villarrubia, Paul G, Muller, K. Paul, Wood, Michael Hemsley, Xiang, Hua, Anderson, Karl Evan Smock, Gay, Daniel Arthur, Bowen, Michael Alexander, Shum, Chung-Lung K, Stuecheli, Erica, Darden, Randall J
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
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Beschreibung
Zusammenfassung:	A method, system, and computer program product for bit flip aware latch placement in integrated circuit generation are provided. The method identifies a chip design for an integrated circuit. A set of chip design constraints, associated with the chip design, is identified. A set of checking groups, associated with a plurality of latches to be placed in the chip design, is determined. Based on the set of chip design constraints and the set of checking groups, a placement scheme for the plurality of latches is selected. The method places the plurality of latches within the chip design based on the placement scheme and the set of checking groups.