SEMICONDUCTOR MEMORY DEVICE

A memory plane region includes a first structure and a second structure having conductive layers, and includes a first memory region to a third memory region, a first region between the first memory region and the second memory region, and a second region between the second memory region and the third memory region. The first structure comprises first via contact electrodes in the first region. The second structure comprises second via contact electrodes in the second region. The first via contact electrodes are electrically connected to transistors provided at positions where the first structure and the first region overlap, and where the second structure and the first region overlap. The second via contact electrodes are electrically connected to transistors provided at positions where the first structure and the second region overlap, and where the second structure and the second region overlap.