SELF-ALIGNED GATE ENDCAP (SAGE) ARCHITECTURES WITHOUT FIN END GAP

Self-aligned gate endcap (SAGE) architectures without fin end gaps, and methods of fabricating self-aligned gate endcap (SAGE) architectures without fin end gaps, are described. In an example, an integrated circuit structure includes a semiconductor fin having a cut along a length of the semiconduct...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: CLENDENNING, Scott B, BAUMGARTEL, Lukas, CHIKKADI, Kiran, LANCASTER, Diane, MITAN, Martin M, Liao, Szuya S, GSTREIN, Florian, METZ, Matthew V, HOURANI, Rami, TORRES, Jessica
Format: Patent
Sprache:eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator CLENDENNING, Scott B
BAUMGARTEL, Lukas
CHIKKADI, Kiran
LANCASTER, Diane
MITAN, Martin M
Liao, Szuya S
GSTREIN, Florian
METZ, Matthew V
HOURANI, Rami
TORRES, Jessica
description Self-aligned gate endcap (SAGE) architectures without fin end gaps, and methods of fabricating self-aligned gate endcap (SAGE) architectures without fin end gaps, are described. In an example, an integrated circuit structure includes a semiconductor fin having a cut along a length of the semiconductor fin. A gate endcap isolation structure has a first portion parallel with the length of the semiconductor fin and is spaced apart from the semiconductor fin. The gate endcap isolation structure also has a second portion in a location of the cut of the semiconductor fin and in contact with the semiconductor fin.
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2024088143A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2024088143A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2024088143A13</originalsourceid><addsrcrecordid>eNrjZHAMdvVx03X08XT3c3VRcHcMcVVw9XNxdgxQ0Ah2dHfVVHAMcvbwDHF1DgkNcg1WCPcM8fAPDVFw8_QDqQNqCOBhYE1LzClO5YXS3AzKbq4hzh66qQX58anFBYnJqXmpJfGhwUYGRiYGFhaGJsaOhsbEqQIAL_krOg</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>SELF-ALIGNED GATE ENDCAP (SAGE) ARCHITECTURES WITHOUT FIN END GAP</title><source>esp@cenet</source><creator>CLENDENNING, Scott B ; BAUMGARTEL, Lukas ; CHIKKADI, Kiran ; LANCASTER, Diane ; MITAN, Martin M ; Liao, Szuya S ; GSTREIN, Florian ; METZ, Matthew V ; HOURANI, Rami ; TORRES, Jessica</creator><creatorcontrib>CLENDENNING, Scott B ; BAUMGARTEL, Lukas ; CHIKKADI, Kiran ; LANCASTER, Diane ; MITAN, Martin M ; Liao, Szuya S ; GSTREIN, Florian ; METZ, Matthew V ; HOURANI, Rami ; TORRES, Jessica</creatorcontrib><description>Self-aligned gate endcap (SAGE) architectures without fin end gaps, and methods of fabricating self-aligned gate endcap (SAGE) architectures without fin end gaps, are described. In an example, an integrated circuit structure includes a semiconductor fin having a cut along a length of the semiconductor fin. A gate endcap isolation structure has a first portion parallel with the length of the semiconductor fin and is spaced apart from the semiconductor fin. The gate endcap isolation structure also has a second portion in a location of the cut of the semiconductor fin and in contact with the semiconductor fin.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2024</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20240314&amp;DB=EPODOC&amp;CC=US&amp;NR=2024088143A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20240314&amp;DB=EPODOC&amp;CC=US&amp;NR=2024088143A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>CLENDENNING, Scott B</creatorcontrib><creatorcontrib>BAUMGARTEL, Lukas</creatorcontrib><creatorcontrib>CHIKKADI, Kiran</creatorcontrib><creatorcontrib>LANCASTER, Diane</creatorcontrib><creatorcontrib>MITAN, Martin M</creatorcontrib><creatorcontrib>Liao, Szuya S</creatorcontrib><creatorcontrib>GSTREIN, Florian</creatorcontrib><creatorcontrib>METZ, Matthew V</creatorcontrib><creatorcontrib>HOURANI, Rami</creatorcontrib><creatorcontrib>TORRES, Jessica</creatorcontrib><title>SELF-ALIGNED GATE ENDCAP (SAGE) ARCHITECTURES WITHOUT FIN END GAP</title><description>Self-aligned gate endcap (SAGE) architectures without fin end gaps, and methods of fabricating self-aligned gate endcap (SAGE) architectures without fin end gaps, are described. In an example, an integrated circuit structure includes a semiconductor fin having a cut along a length of the semiconductor fin. A gate endcap isolation structure has a first portion parallel with the length of the semiconductor fin and is spaced apart from the semiconductor fin. The gate endcap isolation structure also has a second portion in a location of the cut of the semiconductor fin and in contact with the semiconductor fin.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2024</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZHAMdvVx03X08XT3c3VRcHcMcVVw9XNxdgxQ0Ah2dHfVVHAMcvbwDHF1DgkNcg1WCPcM8fAPDVFw8_QDqQNqCOBhYE1LzClO5YXS3AzKbq4hzh66qQX58anFBYnJqXmpJfGhwUYGRiYGFhaGJsaOhsbEqQIAL_krOg</recordid><startdate>20240314</startdate><enddate>20240314</enddate><creator>CLENDENNING, Scott B</creator><creator>BAUMGARTEL, Lukas</creator><creator>CHIKKADI, Kiran</creator><creator>LANCASTER, Diane</creator><creator>MITAN, Martin M</creator><creator>Liao, Szuya S</creator><creator>GSTREIN, Florian</creator><creator>METZ, Matthew V</creator><creator>HOURANI, Rami</creator><creator>TORRES, Jessica</creator><scope>EVB</scope></search><sort><creationdate>20240314</creationdate><title>SELF-ALIGNED GATE ENDCAP (SAGE) ARCHITECTURES WITHOUT FIN END GAP</title><author>CLENDENNING, Scott B ; BAUMGARTEL, Lukas ; CHIKKADI, Kiran ; LANCASTER, Diane ; MITAN, Martin M ; Liao, Szuya S ; GSTREIN, Florian ; METZ, Matthew V ; HOURANI, Rami ; TORRES, Jessica</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2024088143A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2024</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>CLENDENNING, Scott B</creatorcontrib><creatorcontrib>BAUMGARTEL, Lukas</creatorcontrib><creatorcontrib>CHIKKADI, Kiran</creatorcontrib><creatorcontrib>LANCASTER, Diane</creatorcontrib><creatorcontrib>MITAN, Martin M</creatorcontrib><creatorcontrib>Liao, Szuya S</creatorcontrib><creatorcontrib>GSTREIN, Florian</creatorcontrib><creatorcontrib>METZ, Matthew V</creatorcontrib><creatorcontrib>HOURANI, Rami</creatorcontrib><creatorcontrib>TORRES, Jessica</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>CLENDENNING, Scott B</au><au>BAUMGARTEL, Lukas</au><au>CHIKKADI, Kiran</au><au>LANCASTER, Diane</au><au>MITAN, Martin M</au><au>Liao, Szuya S</au><au>GSTREIN, Florian</au><au>METZ, Matthew V</au><au>HOURANI, Rami</au><au>TORRES, Jessica</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>SELF-ALIGNED GATE ENDCAP (SAGE) ARCHITECTURES WITHOUT FIN END GAP</title><date>2024-03-14</date><risdate>2024</risdate><abstract>Self-aligned gate endcap (SAGE) architectures without fin end gaps, and methods of fabricating self-aligned gate endcap (SAGE) architectures without fin end gaps, are described. In an example, an integrated circuit structure includes a semiconductor fin having a cut along a length of the semiconductor fin. A gate endcap isolation structure has a first portion parallel with the length of the semiconductor fin and is spaced apart from the semiconductor fin. The gate endcap isolation structure also has a second portion in a location of the cut of the semiconductor fin and in contact with the semiconductor fin.</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng
recordid cdi_epo_espacenet_US2024088143A1
source esp@cenet
subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title SELF-ALIGNED GATE ENDCAP (SAGE) ARCHITECTURES WITHOUT FIN END GAP
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-06T08%3A13%3A45IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=CLENDENNING,%20Scott%20B&rft.date=2024-03-14&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS2024088143A1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true