Redundant Computations using Integrated Circuit Devices having Analog Inference Capability

A device configured with redundant computations to improve reliability of using memory cells to perform operations of multiplication and accumulation. The device can have a memory cell array and a logic circuit. Each respective memory cell in the memory cell array has a threshold voltage programmable in a first mode to perform operations of multiplication and accumulation and programmable in a second mode, different from the first mode, to store data. The memory cell array has a plurality of regions operable in parallel to perform redundant operations of multiplication and accumulation. The logic circuit is configured to compare a plurality of results, generated from the redundant operations of multiplication and accumulation performed using the plurality of regions respectively, to select an output result from the plurality of results.